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motorola semiconductor technical data dsp56603 order this document by: dsp56603/d ?996 motorola, inc. advance information this document contains information on a new product. specifications and information herein are subject to change without notice. 16-bit digital signal processor the dsp56603 is designed specifically for low-power digital cellular subscriber applications and can perform a wide variety of fixed-point digital signal processing algorithms. the dsp56603 is a member of the dsp56600 core family of 16-bit programmable cmos digital signal processors (dsps). the dsp56600 core can execute one instruction per clock cycle. this 60-mhz chip is optimized for processing-intensive, yet cost-effective, low power consumption digital mobile communications applications. because the dsp56603 provides on-chip program and data ram, as well as the ability to switch sections of this memory between program and data memory, it is also suitable for use as a development platform. figure 1 provides a block diagram of the dsp56603, showing the core structures and the expansion areas. the dsp56600 core includes the data arithmetic and logic unit (alu), address generation unit (agu), program controller, program patch detector, bus interface unit, on-chip emulation (once) module, jtag port, and a phase lock loop (pll)-based clock generator. the expansion areas provide the switchable program and data memories, as well as a versatile set of on-chip peripherals and external ports. figure 1 dsp56603 block diagram extal bootstrap rom 3072 24 program ram 16.5 k 24 yab xab pab ydb xdb pdb gdb modc/ irqc modd/ irqd address 4 data control 6 16 24 16 y memory ram 8192 16 memory peripheral ym_eb xm_eb pm_eb expansion area 6 jtag 5 reset modb/ irqb pcap 3 once clkout x memory ram 8192 16 dsp56600 16-bit core pio_eb area expansion moda/ irqa pinit/ nmi aa0529 de power manage- ment data alu 16 16 + 40 ? 40-bit mac two 40-bit accumulators 40-bit barrel shifter external bus interface program interrupt controller program decode controller program address generator program patch detector address generation unit internal data bus switch clock generator pll triple timer or gpio pins dedicated gpio pins host interface hi08 or gpio pins ssi interface or gpio pins
table of contents ii dsp56603/d, preliminary motorola table of contents section 1 signal/connection descriptions . . . . . . . . . . . . . . . . . . 1-1 section 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 section 3 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 section 4 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 section 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 appendix a power consumption benchmark . . . . . . . . . . . . . . . . . . a-1 data sheet conventions this data sheet uses the following conventions: overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?sserted a high true (active high) signal is high or a low true (active low) signal is low. ?easserted a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications.
data sheet conventions motorola dsp56603/d, preliminary iii dsp56603 features digital signal processing core high-performance dsp56600 core up to 60 million instructions per second (mips) at 2.7?.3 v fully pipelined 16 16-bit parallel multiply-accumulator (mac) two 40-bit accumulators including extension bits 40-bit parallel barrel shifter highly parallel instruction set with unique dsp addressing modes code-compatible with the dsp56300 core position-independent code support user-selectable stack extension nested hardware do loops fast auto-return interrupts on-chip support for software patching and enhancements on-chip phase lock loop (pll) circuit real-time trace capability via external address bus on-chip emulator (once) module and jtag port memory switch mode memory allows reconfiguring program, x-data, and y-data ram sizes switch mode off 16.5 k 24-bit program ram 8 k 16-bit x-data ram 8 k 16-bit y-data ram switch mode on 11.5 k 24-bit program ram 10.5 k 16-bit x-data ram 10.5 k 16-bit y-data ram 3 k 24-bit bootstrap rom
data sheet conventions iv dsp56603/d, preliminary motorola off-chip expansion for both program fetch and program data transfers no additional logic needed for interface to external sram memories peripheral circuits three dedicated general purpose input/output (gpio) pins and as many as thirty- one additional gpio pins (user-selectable as peripherals or gpio pins) host interface (hi08) support: one 8-bit parallel port (or as many as sixteen additional gpio pins) direct interface to motorola hc11, hitachi h8, 8051 family, thomson p6 family minimal logic interface to standard isa bus, motorola 68k family, and intel x86 microprocessor family. synchronous serial interface (ssi) support: two 6-pin ports (or twelve additional gpio pins) supports serial devices with one or more industry-standard codecs, other dsps, microprocessors, and motorola spi-compliant peripherals independent transmitter and receiver sections and a common ssi clock generator network mode using frame sync and up to 32 time slots 8-bit, 12-bit, and 16-bit data word lengths three programmable timers (or as many as three additional gpio pins) three external interrupt/mode control lines one external reset pin for hardware reset energy efficient design very low power cmos design operating voltage range: 1.8 v to 3.3 v < 0.85 ma/mips at 2.7 v < 0.55 ma/mips at 1.8 v low power wait for interrupt standby mode, and ultra low power stop standby mode fully static, hcmos design for operating frequencies from 60 mhz down to dc special power management circuitry
for the latest information motorola dsp56603/d, preliminary v product documentation the three documents listed in table 1 are required for a complete description of the dsp56603 and are necessary to design properly with the part. documentation is available from a local motorola distributor, a motorola semiconductor sales office, a motorola literature distribution center, or through the motorola dsp home page on the internet (the source for the latest information). for the latest information refer to the back cover of this document for: motorola contact addresses motorola mfax service motorola dsp internet address motorola dsp helpline the mfax service and the dsp internet connection maintain the most current specifications, documents, and drawings. these two services are available on demand 24 hours a day. table 1 dsp56602 chip documentation topic description order number dsp56600 family manual detailed description of the 56600-family architecture, and 16-bit dsp core processor and the instruction set dsp56600fm/ad dsp56603 user? manual detailed description of memory, peripherals, and interfaces of the dsp56603 dsp5660 3um/ad dsp56603 technical data electrical and timing specifications, pin descriptions, and package descriptions dsp56603/d
motorola dsp56603/d, preliminary 1-1 section 1 signal/connection descriptions introduction the input and output signals of the dsp56603 are organized into functional groups, as shown in table 1-1 and as illustrated in figure 1-1 . in table 1-2 through table 1-12 , each table row describes the signal or signals present on a pin. the dsp56603 is operated from a 3 v supply; however, some of the inputs can tolerate 5 v. a special notice for this feature is added to the signal descriptions of those inputs. table 1-1 functional group signal allocations functional group number of signals detailed description power (v cc ) 19 table 1-2 ground (gnd) 19 table 1-3 pll and clock signals 5 table 1-4 interrupt and mode control 5 table 1-5 external memory port (also referred to as port a) address bus 16 table 1-6 data bus 24 bus control 4 host interface (hi08) port b (gpio) 16 table 1-7 synchronous serial interface 0 (ssi0) port c (gpio) 6 table 1-8 synchronous serial interface 1 (ssi1) port d (gpio) 6 table 1-9 general purpose input/output (gpio) 3 table 1-10 triple timer 3 table 1-11 jtag/on-chip emulation (once) module 6 table 1-12
signal/connection descriptions introduction 1-2 dsp56603/d, preliminary motorola note: 1. the hi08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (ds), and single or double host request (hr) configurations. since each these modes is configured independently, any combination of these modes is possible. the hi08 signals can also be configured alternately as gpio signals (pb0?b15). 2. the ssi0 and ssi1 signals can be configured alternatively as port c gpio signals (pc0?c5) and port d gpio signals (pd0?d5), respectively. 3. tio0?io2 can be configured alternatively as gpio signals. figure 1-1 dsp56603 signals identified by functional group dsp56603 24 16 external address bus external data bus external bus control synchronous serial interface port 0 (ssi0) 2 port c timers 3 clock/pll jtag/once port power inputs: address bus bus control data bus hi08 pll internal logic high-voltage internal logic low-voltage ssi/gpio/timer a0?15 d0?23 r d wr at mcs tck tdi tdo tms trst de clkout pcap pinit/nmi v cca v ccc v ccd v cch v ccp v ccqh v ccql v ccs 3 dedicated general purpose input/ output port (gpio) 2 4 4 3 grounds: address bus bus control data bus hi08 pll pll internal logic ssi/gpio/timer gnd a gnd c gnd d gnd h gnd p gnd p1 gnd q gnd s 4 4 4 2 interrupt/ mode control moda/irqa modb/irqb modc/irqc modd/irqd reset host interface (hi08) port 1 port b gpio0 gpio1 gpio2 sc00?c02 sck0 srd0 std0 tio0 tio1 tio2 8 3 aa0355 2 extal xtal synchronous serial interface port 1 (ssi1) 2 port d sc10?c12 sck1 srd1 std1 3 had0?ad7 ha0/has ha1/ha8 ha2/ha9 hcs /ha10 hrw/hrd hds /h w r hreq /htrq hack /hrrq port a 4
signal/connection descriptions power motorola dsp56603/d, preliminary 1-3 power table 1-2 power inputs signal name (number of pins) signal description v cca (3) address bus power v cca is an isolated power for sections of address bus i/o drivers, and must be tied externally to all other chip power inputs, except for the v ccql input. the user must provide adequate external decoupling capacitors. v ccc (1) bus control power ? ccc is an isolated power for the bus control i/o drivers, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. v ccd (4) data bus power ? ccd is an isolated power for sections of data bus i/o drivers, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. v cch (1) host power v cch is an isolated power for the hi08 logic, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. v ccp (1) pll power ? ccp is v cc dedicated for phase lock loop (pll) use. the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. v ccqh (3) quiet power high-voltage ? ccqh is an isolated power for the cpu logic, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors. the voltage supplied to these inputs should equal the voltage supplied to i/o power inputs v cca , v ccc , v ccd , v cch , and v ccs . v ccql (4) quiet power low-voltage v ccql is an isolated power for the cpu logic, and should not be tied to the other chip power inputs. the user must provide adequate external decoupling capacitors. v ccs (2) ssis, gpio and timers power ? ccs is a isolated power for the ssis, gpio, and timers logic, and must be tied to all other chip power inputs externally, except for the v ccql input. the user must provide adequate external decoupling capacitors.
signal/connection descriptions ground 1-4 dsp56603/d, preliminary motorola ground table 1-3 grounds signal name (number of pins) signal description gnd a (4) address bus ground ?nd a is an isolated ground for sections of address bus i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd c (2) bus control ground ?nd c is an isolated ground for the bus control i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd d (4) data bus ground ?nd d is an isolated ground for sections of the data bus i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd h (1) host ground ?nd h is an isolated ground for the hi08 i/o drivers, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd p (1) pll ground ?nd p is ground dedicated for pll use, and should be provided with an extremely low impedance path to ground. v ccp should be bypassed to gnd p with a 0.1 m f capacitor located as close as possible to the chip package. gnd p1 (1) pll ground 1 ?nd p1 is ground dedicated for pll use, and should be provided with an extremely low impedance path to ground. gnd q (4) quiet ground ?nd q is an isolated ground for the cpu logic, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd s (2) ssis, gpio, and timers ground gnd s is an isolated ground for the ssis, gpio, and timers logic, and must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors.
signal/connection descriptions clock and phase lock loop motorola dsp56603/d, preliminary 1-5 clock and phase lock loop table 1-4 clock and pll signals signal name signal type state during reset signal description extal input input external clock/crystal input extal interfaces the internal crystal oscillator input to an external crystal or an external clock. xtal output chip- driven crystal output ?tal connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected. pcap input indeter- minate pll capacitor ?cap is an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap may be tied to v cc , gnd, or left floating. clkout output chip- driven clock output clkout provides an output clock synchronized to the internal core clock phase. when the pll is enabled, the division factor (df) equals one, and the multiplication factor (mf) is less than or equal to four, clkout is also synchronized to extal. when the pll is disabled, the clkout frequency is half the frequency of extal. pinit/ nmi input input pll initial/non-maskable interrupt ?uring assertion of reset , the value of pinit/nmi is written into the pll enable (pen) bit of the pll control register 1 (pctl1) , determining whether the pll is enabled or disabled. after reset deassertion and during normal instruction processing, the pinit/nmi schmitt-trigger input is a negative-edge-triggered non-maskable interrupt (nmi) request internally synchronized to clkout. this input can tolerate 5 v.
signal/connection descriptions interrupt and mode control 1-6 dsp56603/d, preliminary motorola interrupt and mode control table 1-5 interrupt and mode control signals signal name signal type state during reset signal description reset input input reset ?eset is an active low, schmitt-trigger input. deassertion of the reset signal is internally synchronized to the clock out (clkout). when asserted, the chip is placed in the reset state and the internal phase generator is reset. the schmitt-trigger input allows a slowly rising input, such as a capacitor charging, to reliably reset the chip. if the reset signal is deasserted synchronous to clkout, exact start-up timing is guaranteed, allowing multiple processors to start up synchronously and operate together. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. in addition, the value on the pinit/nmi pin is latched to the pen bit in the pctl1 register. this input can tolerate 5 v. moda/ irqa input input mode select a/external interrupt request a moda/irqa is an active low schmitt-trigger input, internally synchronized to clkout. moda/irqa selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative- edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the operating mode register (omr) when the reset signal is deasserted. if irqa is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqa to exit the wait state. if the processor is in the stop standby state and irqa is asserted, the processor exits the stop state. this input can tolerate 5 v.
signal/connection descriptions interrupt and mode control motorola dsp56603/d, preliminary 1-7 modb/ irqb input input mode select b/external interrupt request b ?odb/irqb is an active low schmitt-trigger input, internally synchronized to clkout. modb/irqb selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative- edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the omr when the reset signal is deasserted. if irqb is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqb to exit the wait state. this input can tolerate 5 v. modc/ irqc input input mode select c/external interrupt request c ?odc/irqc n is an active low schmitt-trigger input, internally synchronized to clkout. modc/irqc selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative- edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of sixteen initial chip operating modes latched into the omr when the reset signal is deasserted. if irqc is asserted synchronous to clkout, multiple processors can be resynchronized using the wait instruction and asserting irqc to exit the wait state. this input can tolerate 5 v. modd/ irqd input input mode select d/external interrupt request d modd/irqd is an active low schmitt-trigger input, internally synchronized to clkout. modd/irqd selects the initial chip operating mode during hardware reset and becomes a level- sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. moda, modb, modc, and modd select one of sixteen initial chip operating modes, latched into omr when the reset signal is deasserted. if irqd is asserted synchronous to clkout, multiple processors can be re-synchronized using the wait instruction and asserting irqd to exit the wait state. this input can tolerate 5 v. table 1-5 interrupt and mode control signals (continued) signal name signal type state during reset signal description
signal/connection descriptions expansion port (port a) 1-8 dsp56603/d, preliminary motorola expansion port (port a) table 1-6 expansion port, port a signals signal name signal type state during reset signal description a0?15 output set according to chip operating mode 1 address bus ?hese active high outputs specify the address for external program memory accesses. to minimize power dissipation, a0?15 do not change state when external memory spaces are not being accessed. d0?23 bi-directional tri-stated data bus these active high, bidirectional input/outputs provide the bidirectional data bus for external program memory accesses. d0?23 are tri-stated when no external bus activity occurs. mcs output pulled high internally memory chip select ?his signal is an active low output, and is asserted when an external memory access occurs. rd output pulled high internally read enable ?his signal is an active low output. rd is asserted to read external memory on the data bus (d0?23). wr output pulled high internally write enable ?his signal is an active low output. wr is asserted to write external memory on the data bus (d0?23). at output pulled high internally address tracing ?his signal is an active low output. at is asserted (for half of a clock cycle) whenever a new address is driven on the address bus (a0?15) in the program address tracing mode. the new address is either a reflection of internal fetch or internal program space move instruction or an external address driven for an external access. note: 1. the a0?15 pins are asserted according to the selected chip operating mode, as determined by the values on the moda?odd pins. each mode has a different reset address. a0?15 are latched to the value of that reset address minus 1. for example, if the reset address for a selected operating mode is $0800, the address bus is asserted to $07ff.
signal/connection descriptions host interface (hi08) motorola dsp56603/d, preliminary 1-9 host interface (hi08) the hi08 provides a fast parallel data to 8-bit port that can be connected directly to the host bus. the hi08 supports a variety of standard buses, and can be directly connected to a number of industry standard microcomputers, microprocessors, dsps, and dma hardware. the direction and polarity of all pins on the hi08 is programmable. all pins also have programmable gpio functionality. table 1-7 host interface signals signal name signal type state during reset signal description had0 had7 bi-directional bi-directional input or output tri- stated host data bus when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, these signals are lines 0? of the host data bidirectional tri-state bus (hd0?d7). host address and data bus when the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, these signals are lines 0? of the host address/data multiplexed bidirectional tri-state bus (had0?ad7). port b 0? ?hen the hi08 is configured as gpio through the hi08 port control register (hpcr), these signals are individually programmed as inputs or outputs through the hi08 data direction register (hddr). when configured as an input, this pin can tolerate 5 v. ha0/ has input input input or output tri- stated host address input 0 when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus (ha0). host address strobe when the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has ) schmitt-trigger input. the polarity of the address strobe is programmable. port b 8 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v.
signal/connection descriptions host interface (hi08) 1-10 dsp56603/d, preliminary motorola ha1/ha8 input input input or output tri- stated host address input 1 when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line one of the host address input bus (ha1). host address 8 when the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line eight of the input host address bus (ha8). port b 9 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. ha2/ha9 input input input or output tri- stated host address input 2 when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is line two of the host address input bus (ha2). host address 9 when the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line nine of the input host address bus (ha9). port b 10 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. table 1-7 host interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions host interface (hi08) motorola dsp56603/d, preliminary 1-11 hrw/hrd input input input or output tri- stated host read/write ?hen the hi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the read/write input (hrw). host read data ?hen the hi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the read data strobe schmitt-trigger input (hrd ). the polarity of the data strobe is programmable. port b 11 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. hds /hwr input input input or output tri- stated host data strobe when the hi08 is programmed to interface a single-data-strobe host bus and the hi function is selected, this signal is the host data strobe schmitt- trigger input (hds ). the polarity of the data strobe is programmable. host write enable when the hi08 is programmed to interface a double-data-strobe host bus and the hi function is selected, this signal is the write data strobe schmitt-trigger input (hwr ). the polarity of the data strobe is programmable. port b 12 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. table 1-7 host interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions host interface (hi08) 1-12 dsp56603/d, preliminary motorola hcs /ha10 input input input or output tri- stated host chip select when the hi08 is programmed to interface a non-multiplexed host bus and the hi function is selected, this signal is the host chip select input (hcs ). the polarity of the chip select is programmable. host address 10 when the hi08 is programmed to interface a multiplexed host bus and the hi function is selected, this signal is line 10 of the input host address bus (ha10). port b 13 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. hreq / htrq output output input or output tri- stated host request when the hi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host request output (hreq ). the polarity of the host request is programmable. the host request can be programmed as a driven or open-drain output. transmit host request when the hi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the transmit host request output (htrq ). the polarity of the host request is programmable. the host request can be programmed as a driven or open-drain output. port b 14 ?hen the hi08 is programmed to interface a multiplexed host bus and the signal is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. table 1-7 host interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions host interface (hi08) motorola dsp56603/d, preliminary 1-13 hack / hrrq input output input or output tri- stated host acknowledge when the hi08 is programmed to interface a single host request host bus and the hi function is selected, this signal is the host acknowledge schmitt-trigger input (hack ). the polarity of the host acknowledge is programmable. receive host request when the hi08 is programmed to interface a double host request host bus and the hi function is selected, this signal is the receive host request output (hrrq ). the polarity of the host request is programmable. the host request can be programmed as a driven or open-drain output. port b 15 ?hen the hi08 is configured as gpio through the hpcr, this signal is individually programmed as an input or output through the hddr. when configured as an input, this pin can tolerate 5 v. table 1-7 host interface signals (continued) signal name signal type state during reset signal description
signal/connection descriptions synchronous serial interface 0 (ssi0) 1-14 dsp56603/d, preliminary motorola synchronous serial interface 0 (ssi0) two identical synchronous serial interfaces (ssi0 and ssi1) provide a full-duplex serial port for serial communication with a variety of serial devices including one or more industry-standard codecs, other dsps, or microprocessors. when either ssi port is disabled, it can be used for general purpose i/o (gpio). table 1-8 synchronous serial interface 0 (ssi0) signal name signal type state during reset signal description sc00 input or output input or output tri- stated serial control signal 0 ?he function of sc00 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for or for serial i/o flag 0. port c 0 ?hen configured as pc0, signal direction is controlled through the ssi0 port direction control register (prrc). the signal can be configured as ssi signal sc00 through the ssi0 port control register (pcrc). when configured as an input, this pin can tolerate 5 v. sc01 input or output input or output tri- stated serial control signal 1 the function of sc00 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for serial i/o flag 1. port c 1 ?hen configured as pc1, signal direction is controlled through the prrc. the signal can be configured as an ssi signal sc01 through the pcrc. when configured as an input, this pin can tolerate 5 v.
signal/connection descriptions synchronous serial interface 0 (ssi0) motorola dsp56603/d, preliminary 1-15 sc02 input or output input or output tri- stated serial control signal 2 sc02 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c 2 ?hen configured as pc2, signal direction is controlled through the prrc. the signal can be configured as an ssi signal sc02 through the pcrc. when configured as an input, this pin can tolerate 5 v. sck0 input or output input or output tri- stated serial clock ?ck0 is a bidirectional schmitt-trigger input signal providing the serial bit rate clock for the ssi interface. the sck0 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (i.e., the system clock frequency must be at least three times the external ssi clock frequency). the ssi needs at least three dsp phases inside each half of the serial clock. port c 3 ?hen configured as pc3, signal direction is controlled through the prrc. the signal can be configured as an ssi signal sck0 through the pcrc. when configured as an input, this pin can tolerate 5 v. srd0 input input or output tri- stated serial receive data ?rd0 receives serial data and transfers the data to the ssi receive shift register. port c 4 ?hen configured as pc4, signal direction is controlled through the prrc. the signal can be configured as an ssi signal srd0 through the pcrc. when configured as an input, this pin can tolerate 5 v. table 1-8 synchronous serial interface 0 (ssi0) (continued) signal name signal type state during reset signal description
signal/connection descriptions synchronous serial interface 0 (ssi0) 1-16 dsp56603/d, preliminary motorola std0 output input or output tri- stated serial transmit data std0 is used for transmitting data from the ssi transmit shift register. port c 5 ?hen configured as pc5, signal direction is controlled through the prrc. the signal can be configured as an ssi signal std0 through the pcrc. when configured as an input, this pin can tolerate 5 v. table 1-8 synchronous serial interface 0 (ssi0) (continued) signal name signal type state during reset signal description
signal/connection descriptions synchronous serial interface 1 (ssi1) motorola dsp56603/d, preliminary 1-17 synchronous serial interface 1 (ssi1) table 1-9 synchronous serial interface 1 (ssi1) signal name signal type state during reset signal description sc10 input or output input or output tri- stated serial control signal 0 ?he function of sc10 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for or for serial i/o flag 0. port d 0 ?hen configured as pd0, signal direction is controlled through the ssi1 port direction control register (prrd). the signal can be configured as ssi signal sc10 through the ssi1 port control register (pcrd). when configured as an input, this pin can tolerate 5 v. sc11 input or output input or output tri- stated serial control signal 1 the function of sc11 is determined by the selection of either synchronous or asynchronous mode. for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used for serial i/o flag 1. port d 1 ?hen configured as pd1, signal direction is controlled through the prrd. the signal can be configured as an ssi signal sc11 through the pcrd. when configured as an input, this pin can tolerate 5 v. sc12 input or output input or output tri- stated serial control signal 2 sc12 is used for frame sync i/o. sc12 is the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d 2 ?hen configured as pd2, signal direction is controlled through the prrd. the signal can be configured as an ssi signal sc12 through the pcrd. when configured as an input, this pin can tolerate 5 v.
signal/connection descriptions synchronous serial interface 1 (ssi1) 1-18 dsp56603/d, preliminary motorola sck1 input or output input or output tri- stated serial clock ?ck1 is a bidirectional schmitt-trigger input signal providing the serial bit rate clock for the ssi interface. the sck1 is a clock input or output used by both the transmitter and receiver in synchronous modes, or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (i.e., the system clock frequency must be at least three times the external ssi clock frequency). the ssi needs at least three dsp phases inside each half of the serial clock. port d 3 ?hen configured as pd3, signal direction is controlled through the prrd. the signal can be configured as an ssi signal sck1 through the pcrd. when configured as an input, this pin can tolerate 5 v. srd1 input input or output tri- stated serial receive data ?rd1 receives serial data and transfers the data to the ssi receive shift register. port d 4 ?hen configured as pd4, signal direction is controlled through the prrd. the signal can be configured as an ssi signal srd1 through the pcrd. when configured as an input, this pin can tolerate 5 v. std1 output input or output tri- stated serial transmit data std1 is used for transmitting data from the ssi transmit shift register. port d 5 ?hen configured as pd5, signal direction is controlled through the prrd. the signal can be configured as an ssi signal std1 through the pcrd. when configured as an input, this pin can tolerate 5 v. table 1-9 synchronous serial interface 1 (ssi1) (continued) signal name signal type state during reset signal description
signal/connection descriptions general purpose i/o, gpio motorola dsp56603/d, preliminary 1-19 general purpose i/o, gpio three dedicated general purpose input/output (gpio) signals are provided on the dsp56603. each is reconfigurable as input, output, or tri-state. these signals are exclusively defined as gpio, and do not offer additional functionality. table 1-10 general purpose i/o (gpio) signal name signal type state during reset signal description gpio0 input or output input general purpose i/o when a gpio signal is used as input, the logic state is reflected to an internal register and can be read by the software. when a gpio signal is used as output, the logic state is controlled by the software. this input can tolerate 5 v. gpio1 input or output input general purpose i/o when a gpio signal is used as input, the logic state is reflected to an internal register and can be read by the software. when a gpio signal is used as output, the logic state is controlled by the software. this input can tolerate 5 v. gpio2 input or output input general purpose i/o when a gpio signal is used as input, the logic state is reflected to an internal register and can be read by the software. when a gpio signal is used as output, the logic state is controlled by the software. this input can tolerate 5 v.
signal/connection descriptions triple timer 1-20 dsp56603/d, preliminary motorola triple timer three identical and independent timers are implemented. the three timers can use internal or external clocking and can interrupt the dsp after a specified number of events (clocks), or can signal an external device after counting a specific number of internal events. when a timer port is disabled, it can be used for general purpose i/o (gpio). table 1-11 triple timer signals signal name signal type state during reset signal description tio0 input or output input or output gpio input timer 0 schmitt-trigger input/output when tio0 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. when tio0 is used as an output, the timer module functions as a timer and tio0 provides the timer pulse. when the tio0 is not used by the timer module, it can be used for gpio . when configured as an input, this pin can tolerate 5 v. tio1 input or output input or output gpio input timer 1 schmitt-trigger input/output when tio1 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. when tio1 is used as an output, the timer module functions as a timer and tio1 provides the timer pulse. when tio1 is not used by the timer module, it can be used for gpio. when configured as an input, this pin can tolerate 5 v. tio2 input or output input or output gpio input timer 2 schmitt-trigger input/output when tio2 is used as an input, the timer module functions as an external event counter or measures external pulse width or signal period. when tio2 is used as an output, the timer module functions as a timer and tio2 provides the timer pulse. when tio2 is not used by the timer module, it can be used for gpio . when configured as an input, this pin can tolerate 5 v.
signal/connection descriptions jtag/once interface motorola dsp56603/d, preliminary 1-21 jtag/once interface table 1-12 jtag/on-chip emulation (once) interface signals signal name signal type state during reset signal description tck input input test clock tck is a test clock input signal used to synchronize the jtag test logic. the tck pin can be tri-stated. this input can tolerate 5 v. tdi input input test data input ?tdi is a test data serial input signal used for test instructions and data. tdi is sampled on the rising edge of the tck signal and has an internal pull-up resistor. this input can tolerate 5 v. tdo output tri-state test data output ?tdo is a test data serial output signal used for test instructions and data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of the tck signal. tms input input test mode select ?tms is an input signal used to sequence the test controller? state machine. tms is sampled on the rising edge of the tck signal and has an internal pull-up resistor. this input can tolerate 5 v. trst input input test reset ?rst is an active-low schmitt-trigger input signal used to asynchronously initialize the test controller. t rst has an internal pull-up resistor. trst must be asserted during the power up sequence. this input can tolerate 5 v. de bi-directional input debug event ?e is an open-drain bidirectional active-low signal providing, as an input, a means of entering the debug mode of operation from an external command controller, and as an output, a means of acknowledging that the chip has entered the debug mode. the de has an internal pull-up resistor. when this pin is an input, it can tolerate 5 v.
signal/connection descriptions jtag/once interface 1-22 dsp56603/d, preliminary motorola
motorola dsp56603/d, preliminary 2-1 section 2 specifications general characteristics the dsp56603 is fabricated in high-density cmos with transistor-transistor logic (ttl)-compatible inputs and outputs. functional operating conditions are given in table 2-4 on page 2-3. absolute maximum ratings given in table 2-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. the dsp56603 dc/ac electrical specifications are preliminary and are from design simulations. these specifications may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published after complete characterization and device qualifications have been completed. table 2-1 absolute maximum ratings (gnd = 0 v) rating symbol value unit supply voltage v cc ?.3 to +4 v all input voltages excluding ? volt tolerant?inputs v in gnd ?0.3 to v cc + 0.3 v all ? volt tolerant?inputs voltages 1 v in5 gnd ?0.3 to v cc + 3.95 v current drain per pin excluding v cc and gnd i 10 ma operating temperature range t a ?0 to 85 ?c storage temperature t stg ?5 to +150 ?c note: 1. ? volt tolerant?inputs are inputs that tolerate 5 v. all ? volt tolerant?input voltages cannot be more than 3.95 v greater than supply voltage. this restriction applies to power-on, as well as to normal operation.
specifications general characteristics 2-2 dsp56603/d, preliminary motorola caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either or v cc or gnd). table 2-2 recommended operating conditions rating symbol value unit supply voltage v cc 2.7 to 3.3 v ambient temperature t a ?0 to +85 ?c table 2-3 package thermal characteristics thermal resistance 1 144-pin tqfp symbol value units junction-to-ambient thermal resistance 2 r q ja or q ja 49.3 ?c/w junction-to-case thermal resistance 3 r q jc or q jc 8.2 ?c/w thermal characterization parameter y jt 5.5 ?c/w notes: 1. see discussion under heat dissipation on page 4-1. 2. junction-to-ambient thermal resistance is based on measurements on a horizontal single-sided printed circuit board per semi g38-87 in natural convection. 3. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88, with the exception that the cold plate temperature is used for the case temperature. 4. thermal characterization parameter, y jt , is defined in eia/jesd 51?. it is a measure of the difference in temperature between the junction and a thermocouple on top of the package normalized by the power dissipation. 5. semi is semiconductor equipment and materials international, 805 east middlefield road, mountain view, ca 94043, (415) 964-5111. 6. mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at (800) 854-7179 or (303) 397-7956.
specifications dc electrical characteristics motorola dsp56603/d, preliminary 2-3 dc electrical characteristics (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) table 2-4 dc electrical characteristics for the dsp56603 characteristics symbol min typ max unit supply voltage for v cca , v ccc , v ccd , v cch , v ccp , v ccqh , v ccql , and v ccs 1 v cc 2.7 3.0 3.3 v input high voltage d0?23 mod/irq 2 , reset , pinit/nmi , and all jtag/hi08/ssi/timer/gpio pins extal v ih v ihp v ihx 2.0 2.0 v cc ?0.4 v cc 5.75 v cc v v v input low voltage d0?23, mod/irq 2 , reset , pinit/nmi all jtag/hi08/ssi/timer/gpio pins extal v il v ilp v ilx ?.3 ?.3 ?.3 0.8 0.8 0.4 v v v input leakage current i in ?0.0 10.0 m a high-impedance (off state) input current (2.4 v/0.4 v) i tsi ?0.0 10.0 m a output high voltage (i oh = ?.4 ma) v oh 2.4 v output low voltage (i ol = 3.0 ma, open drain pins i ol = 6.7 ma) v ol 0.4 v internal supply current at 60 mhz in normal mode 3, 6 in wait mode 4, 6 in stop mode 5, 6 i cci i ccw i ccs 57 4.6 50 ma ma m a pll supply current in stop mode (pll on) 6 i pll 3.5 ?ma input capacitance 6 c in 10 pf notes: 1. throughout the data sheet, assume that v cca , v ccc , v ccd , v cch , v ccp , v ccqh , v ccql , and v ccs power pins have the same voltage level. 2. this specification applies to moda/irqa , modb/irqb, modc/irqc , and modd/irqd pins. 3. power consumption considerations on page 4-5 provides a formula to compute the estimated current requirements in normal mode. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). measurements are based on synthetic intensive dsp benchmarks (see appendix a ). the power consumption numbers in this specification are 90% of the measured results of this benchmark. this reflects typical dsp applications. typical internal supply current is measured with v cc = 2.7 v at t j = 100?c. the actual current consumption varies with the operating conditions and the program being executed. 4. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). 5. in order to obtain these results, all inputs that are not disconnected at stop mode must be terminated. 6. these values are periodically sampled and not 100% tested.
specifications ac electrical characteristics 2-4 dsp56603/d, preliminary motorola ac electrical characteristics the timing specifications in ac electrical characteristics are tested with a v il maximum of 0.3 v and a v ih minimum of 2.4 v for all pins except extal, which is tested using the input levels set forth in dc electrical characteristics . ac timing specifications referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal? transition. timings specified relative to a clkout edge are measured with respect to the 50% point of the applicable clkout transition. all other dsp56603 output timing specifications are measured with the production test machine v ol and v oh reference levels set at 0.8 v and 2.0 v, respectively. note: unless specifically noted otherwise, all references to clkout edges assume that the pll is enabled. all timings except those that specifically relate to the extal input are guaranteed by test with the pll enabled. ac electrical characteristics?nternal clock operation (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) for each occurrence of t h , t l , t c , or i cyc, substitute the numbers given in table 2-5 . (the terms ef, et h , et l , and et c are described in table 2-6 .) table 2-5 internal clocks characteristics symbol expression internal operation frequency with pll enabled f (ef mf 1 )/(pdf 2 df 3 ) internal operation frequency with pll disabled f ef/2 internal clock high period pll disabled pll enabled and mf 4 pll enabled and mf > 4 t h et c (min) 0.49 et c pdf df/mf (max) 0.51 et c pdf df/mf (min) 0.47 et c pdf df/mf (max) 0.53 et c pdf df/mf internal clock low period pll disabled pll enabled and mf 4 pll enabled and mf > 4 t l et c (min) 0.49 et c pdf df/mf (max) 0.51 et c pdf df/mf (min) 0.47 et c pdf df/mf (max) 0.53 et c pdf df/mf
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-5 ac electrical characteristics?xternal clock operation (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) the dsp56603 system clock can be derived from the on-chip crystal oscillator, or it can be externally supplied. an externally supplied square wave voltage source should be connected to extal, leaving xtal physically not connected to the board or socket (see figure 2-1 on page 2-6). the rise and fall time of this external clock should be 3 ns maximum. internal clock cycle time with pll enabled t c et c pdf df/mf internal clock cycle time with pll disabled t c 2 et c instruction cycle time i cyc t c notes: 1. mf represents the pll multiplication factor. 2. pdf represents the pll predivision factor. 3. df represents the pll division factor. table 2-6 clock operation num characteristics symbol min max unit 1 frequency of extal (extal pin frequency) ef 0 60.0 mhz 2 clock input high 1, 2 pll disabled (46.7?3.3% duty cycle) pll enabled (42.5?7.5% duty cycle, at 60 mhz) et h 7.8 7.1 157.0 m s ns 3 clock input low 1, 2 pll disabled (46.7?3.3% duty cycle) pll enabled (42.5?7.5% duty cycle) et l 7.8 7.1 157.0 m s ns 4 clock cycle time 2 pll disabled pll enabled et c 16.7 16.7 273.1 m s ns 5 clkout change from extal fall, pll disabled 4.3 11.0 ns 6 clkout from extal with pll enabled (mf = pdf df, mf 4, ef > 15 mhz) 4 0 1.8 ns 7 instruction cycle time = i cyc = t c 1, 3 pll disabled pll enabled i cyc 33.3 16.7 8.53 m s ns table 2-5 internal clocks (continued) characteristics symbol expression
specifications ac electrical characteristics 2-6 dsp56603/d, preliminary motorola notes: 1. external clock input high, external clock input low, and clkout are measured at 50% of the signal transition. 2. the maximum value for pll enabled is given for minimum vco and maximum mf. 3. the maximum value for pll enabled is given for minimum vco and maximum df. 4. these timings are periodically sampled and not 100% tested. figure 2-1 crystal oscillator circuits table 2-6 clock operation (continued) num characteristics symbol min max unit suggested component values: f osc = 4 mhz r = 680 k w 10% c = 56 pf 20% f osc = 20 mhz r = 680 k w 10% c = 22 pf 20% calculations were done for a 4/20 mhz crystal with the following parameters: a load capacitance (c l )of 30/20 pf, a shunt capacitance (c 0 ) of 7/6 pf, a series resistance of 100/20 w , and drive level of 2 mw. suggested component values: f osc = 32.768 khz r1 = 3.9 m w 10% r2 = 200 k w 10% c = 22 pf 20% calculations were done for a 32.768 khz crystal with the following parameters: a load capacitance (c l ) of 12.5 pf, a shunt capacitance (c 0 ) of 1.8 pf, a series resistance of 40 k w , and drive level of 1 m w. xtal1 c c r1 fundamental frequency fork crystal oscillator xtal extal xtal1 c c r fundamental frequency crystal oscillator xtal extal r2 aa0458
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-7 ac electrical characteristics?hase lock loop (pll) characteristics (v cc = 3.0 v 0.3 v; t a = ?0? to 85? c, c l = 50 pf + 2 ttl loads) figure 2-2 external clock timing table 2-7 phase lock loop characteristics characteristics expression min max unit vco frequency when pll enabled 1 mf ef 2 / pdf 30 120 mhz pll external capacitor (pcap pin to v ccp ) mf 4 mf > 4 cpcap 2 mf 425 ?125 mf 520 mf 590 ?175 mf 920 pf notes: 1. the vco output is further divided by 2 when pll is enabled. if the division factor (df) is 1, the operating frequency is . 2. cpcap is the value of the pll capacitor (connected between pcap pin and v ccp ). (the recommended value for cpcap is (500 mf ?150) pf for mf 4 and (690 mf) pf for mf > 4.) et h et l et c clkout with pll disabled clkout with pll enabled extal midpoint v ihc 4 5 5 6 7 7 note: the midpoint is 0.5 (v ihc + v ilc ). v ilc 3 2 aa0367 vco 2 -------------
specifications ac electrical characteristics 2-8 dsp56603/d, preliminary motorola ac electrical characteristics?eset, stop, mode select, and interrupt timing (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) ws = number of wait states (measured in clock cycles, number of t c ) table 2-8 reset timing num characteristics expression 60 mhz unit min max 8 delay from reset assertion to all pins at reset value 1 20.0 + t c 333.34 ns 9 required reset duration 2, 3 power on, external clock generator, pll disabled power on, external clock generator, pll enabled power on, internal oscillator during stop, xtal disabled during stop, xtal enabled during normal operation 50 et c 1000 et c 75000 et c 75000 et c 2.5 t c 2.5 t c 833.3 16.72 1.25 1.25 41.7 41.7 ns m s ms ms ns ns 10 delay from asynchronous reset deassertion to first external address output (internal reset deassertion) 4 minimum maximum 3.25 t c + 2.2 20.25t c + 12.1 56.4 349.6 ns ns 11 synchronous reset setup time from reset deassertion to first clkout transition t c 9.0 16.7 ns 12 synchronous reset deassertion, delay time from the first clkout transition to the first external address output minimum maximum 3.25 t c + 1.1 20.25t c + 5.5 55.3 343.0 ns ns notes: 1. these timings are periodically sampled and not 100% tested. 2. for an external clock generator, reset duration is measured during the time in which reset is asserted, v cc is valid, and the extal input is active and valid. for internal oscillator, reset duration is measured during the time in which reset is asserted and v cc is valid. the specified timing reflects the crystal oscillator stabilization time after power-up. this number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. 3. when v cc is powered up and the ?equired reset duration?conditions as specified above are not yet met, the device circuitry is in an uninitialized state that may result in significant power consumption. to minimize power consumption, the dsp56603 should be initialized as soon as possible to limit the duration of the uninitialized state. 4. this specification is valid if the pll does not lose lock.
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-9 figure 2-3 reset timing figure 2-4 synchronous reset timing table 2-9 mode select and interrupt timings num characteristics expression 60 mhz unit min max 13 mode select setup time 30.0 ns 14 mode select hold time 0.0 ns 15 minimum edge-triggered interrupt request assertion width 10.0 ns 16 minimum edge-triggered interrupt request deassertion width 10.0 ns 17 delay from irq or nmi assertion to external memory access address out valid caused by first interrupt instruction fetch caused by first interrupt instruction execution 4.25 t c + 2.2 7.25 t c + 2.2 73.0 123.0 ns ns v ih first fetch 9 10 8 reset a0?15 all pins aa0367 11 clkout reset a0?15 12 aa0368
specifications ac electrical characteristics 2-10 dsp56603/d, preliminary motorola 18 delay from irqa , irqb , irqc , irqd , nmi assertion to general purpose transfer output valid caused by first interrupt instruction execution 10 t c + 5.5 172.2 ns 19 delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 1 3.75 t c + ws t c ?15.4 63.8 ns 20 delay from rd assertion to interrupt request deassertion for level sensitive fast interrupts 1 3.25 t c + ws t c ?15.4 55.4 ns 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts 1 sram ws = 1 sram ws = 2, 3 sram ws 3 4 (3.5 + ws) t c ?15.4 (3.0 + ws) t c ?15.4 (2.5 + ws) t c ?15.4 59.6 51.3 26.3 ns ns ns 22 synchronous interrupt setup time from irqa , irqb , irqc , irqd , nmi assertion to the second clkout transition t c 9.0 16.7 ns 23 synchronous interrupt delay time from clkout? second transition to the first external address output valid caused by the first instruction fetch after coming out of wait minimum maximum 9.25 t c + 1.1 24.75 t c + 5.5 155.3 418.0 ns ns 24 duration for irqa assertion to recover from stop 9.0 ns 25 delay from irqa assertion to fetch of first instruction (when exiting stop) 2, 3 pll not active during stop and stop delay enabled (pctl1 bit 6 = 0, omr bit 6 = 0) pll not active during stop, stop delay not enabled (pctl1 bit 6 = 0, omr bit 6 = 1) pll active during stop, no stop delay (pctl1 bit 6 = 1) plc et c pdf + (128k ?plc/2) t c plc et c pdf + (23.75 0.5) t c plc et c (8.25 0.5) t c 2.2 388.3 ns 129.2 22.6 20.4 ms 145.8 ms ns table 2-9 mode select and interrupt timings (continued) num characteristics expression 60 mhz unit min max
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-11 26 duration of level-sensitive irqa assertion to ensure interrupt service (when exiting stop) 2,3 pll not active during stop, stop delay enabled (pctl1 bit 6 = 0, omr bit 6 = 0) pll not active during stop, stop delay not enabled (pctl1 bit 6 = 0, omr bit 6 = 1) pll active during stop, no stop delay (pctl1 bit 6 = 1) plc et c pdf + (128k ?plc/2) t c plc et c pdf + (20.5 0.5) t c 5.5 t c 22.6 20.4 91.7 ns ns ns 27 interrupt requests rate hi08, ssi, timer irq (edge trigger) irq (level trigger) 12t c 8t c 12t c 200.4 133.6 200.4 ns notes: 1. when using fast interrupts and irqa , irqb , irqc , and irqd are defined as level-sensitive, then timings 14 through 16 apply to prevent multiple interrupt service. to avoid these timing restrictions, the deasserted edge-triggered mode is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive mode. 2. this timing depends on several settings: for pll disabled, using internal oscillator (pll control register (pctl)1 bit 4 = 0) and oscillator disabled during stop (pctl1 bit 5 = 0), a stabilization delay is required to assure the oscillator is stable before executing programs. in that case, resetting the stop delay (omr bit 6 = 0) provides the proper delay. while it is possible to set omr bit 6 = 1, it is not recommended and these specifications do not guarantee timings for that case. for pll disabled, using internal oscillator (pctl1 bit 4 = 0) and oscillator enabled during stop (pctl1 bit 5 = 1), no stabilization delay is required and recovery time is minimal (omr bit 6 setting is ignored). for pll disabled, using external clock (pctl1 bit 4 = 1), no stabilization delay is required and recovery time is defined by the pctl1 bit 6 and omr bit 6 settings. ? for pll disabled, using external clock (pctl1 bit 4 = 1), no stabilization delay is required and recovery time is defined by the pctl1 bit 6 and omr bit 6 settings. ? for pll enabled, if pctl1 bit 6 is 0, the pll is shut down during stop. recovering from stop requires the pll to re-lock. the pll lock procedure duration, plc (pll lock cycles), may be in the range of 0 to 300 cycles. this procedure occurs in parallel to the stop delay counter, and stop recovery ends when the last of these two events occurs (the stop delay counter completes its count, or the pll lock procedure completes). ? plc value for pll disabled is 0. maximum value for et c is 4096 (maximum multiplication factor) divided by the desired internal frequency (i.e., for 60 mhz it is 4096/60 mhz = 68.26 m s). during the stabilization period, t c , t h , and t l will not be constant. their width may vary, so timing may vary as well. 3. these timings are periodically sampled and not 100% tested. table 2-9 mode select and interrupt timings (continued) num characteristics expression 60 mhz unit min max
specifications ac electrical characteristics 2-12 dsp56603/d, preliminary motorola figure 2-5 external level?ensitive fast interrupt timing figure 2-6 external interrupt timing (negative edge-triggered) first interrupt instruction execution/fetch a) first interrupt instruction execution b) general purpose i/o a0?15 rd wr general purpose i/o 20 21 19 17 18 aa0369 irqa , irqb , irqc , irq d , nmi irqa , irqb , irqc , irq d , nmi aa0370 15 16 irqa , irqb , irqc , irq d , nmi irqa , irqb , irq c , irqd , nmi
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-13 figure 2-7 synchronous interrupt from wait timing figure 2-8 operating mode select timing figure 2-9 recovery from stop using irqa figure 2-10 recovery from stop using irqa interrupt service t0, t2 t1, t3 22 23 clkout a0?15 aa0371 irqa irqb , irqc , irq d , nmi v ih v il v ih v il v ih 13 reset moda, modb, modc, modd 14 aa0372 first instruction fetch irqa a0?15, m cs 24 25 aa0373 irqa 26 25 aa0374 first irqa interrupt instruction fetch a0?15, m cs
specifications ac electrical characteristics 2-14 dsp56603/d, preliminary motorola ac electrical characteristics?ort a (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) table 2-10 sram read and write access num characteristics symbol expression 60 mhz unit min max 100 address valid and mcs assertion pulse width ? ws 3 ? ws 7 ws 3 8 t rc , t wc (ws + 1) t c ?4.4 (ws + 2) t c ?4.4 (ws + 3) t c ?4.4 28.9 95.6 178.9 ns 101 address valid and mcs assertion to wr assertion ws = 1 ? ws 3 ws 3 4 t as 0.25 t c ?3.7 0.75 t c ?4.4 1.25 t c ?4.4 0.5 8.1 16.4 ns 102 wr assertion pulse width ws = 1 ? ws 3 ws 3 4 t wp 1.5 t c ?5.7 ws t c ?4.4 (ws ?0.5) t c ?4.4 19.3 28.9 53.9 ns 103 wr deassertion to address invalid and mcs deassertion ? ws 3 ? ws 7 ws 3 8 t wr 0.25 t c ?3.8 1.25 t c ?4.4 2.25 t c ?4.4 0.4 16.4 33.1 ns 104 address and mcs valid to input data valid, ws 3 1 t aa , t ac (ws + 0.75) t c ?8.5 20.7 ns 105 rd assertion to input data valid, ws 3 1 t oe (ws + 0.5) t c ?8.5 16.5 ns 106 rd deassertion to data invalid (data hold time) t ohz 0.0 ns 107 address valid to wr deassertion, ws 3 1 t aw (ws + 0.75) t c ?4.4 24.8 ns 108 data valid to wr deassertion (data setup time), ws 3 1 t ds (t dw ) (ws ?0.25) t c ?3.9 8.6 ns
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-15 109 data hold time from wr deassertion ? ws 3 ? ws 7 ws 3 8 t dh 0.25 t c ?3.8 1.25 t c ?3.8 2.25 t c ?3.8 0.4 17.0 33.7 ns 110 wr assertion to data active ws = 1 ? ws 3 ws 3 4 0.75 t c ?3.7 0.25 t c ?3.7 ?.25 t c ?3.7 8.8 0.5 ?.9 ns 111 wr deassertion to data high impedance ? ws 3 ? ws 7 ws 3 8 0.25 t c + 0.6 1.25 t c + 0.6 2.25 t c + 0.6 4.8 21.4 38.1 ns 112 previous rd deassertion to data active (write) ? ws 3 ? ws 7 ws 3 8 1.25 t c ?4.4 2.25 t c ?4.4 3.25 t c ?4.4 16.4 33.1 49.8 ns 113 rd deassertion time ? ws 3 ? ws 7 ws 3 8 0.75 t c ?4.4 1.75 t c ?4.4 2.75 t c ?4.4 8.1 24.8 41.4 ns 114 wr deassertion time ws = 1 ? ws 3 ? ws 7 ws 3 8 0.5 t c ?3.1 t c ?3.1 2.5 t c ?3.1 3.5 t c ?3.1 5.2 13.6 38.6 55.2 ns 115 address valid to rd assertion 0.5 t c ?4.0 4.3 ns 116 rd assertion pulse width (ws + 0.25) t c ?3.8 17.0 ns 117 rd deassertion to address invalid ? ws 3 ? ws 7 ws 3 8 0.25 t c ?3.0 1.25 t c ?3.0 2.25 t c ?3.0 1.2 17.8 34.5 ns table 2-10 sram read and write access (continued) num characteristics symbol expression 60 mhz unit min max
specifications ac electrical characteristics 2-16 dsp56603/d, preliminary motorola notes: 1. ws refers to the number of wait states, as specified in the bcr. 2. the asynchronous delays specified in the expressions are valid for dsp56603-60. 3. the address trace (at ) pin is also active on accesses to internal program memory if the address trace enable (ate) bit (bit 15) of the omr is set. in this case, the mcs , rd , and wr signals are deasserted and the data bus is tri-stated while the address bus is driven with the address of the internal access. figure 2-11 sram read access table 2-10 sram read and write access (continued) num characteristics symbol expression 60 mhz unit min max a0?15, rd wr data in d0?23 mcs at 100 113 116 115 105 104 250 251 aa0375 117 106
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-17 figure 2-12 sram write access table 2-11 external bus synchronous timings (sram access) num characteristics expression 60 mhz unit min max 198 clkout low to address valid and mcs assertion 0.25 t c + 5.5 9.7 ns 199 clkout low to address invalid and mcs deassertion 0.25 t c 4.2 ns 202 clkout low to data out active 5 0.25 t c 4.2 ns 203 clkout low to data out valid 0.25 t c + 5.5 9.7 ns 204 clkout low to data out invalid 0.25 t c 4.2 ns 205 clkout low to data out high z 5 0.25 t c + 1.1 5.3 ns 206 data in valid to clkout low (setup) 3.0 ns 207 clkout low to data in invalid (hold) 0.0 ns a0?15, wr rd data in d0?23 mcs at 100 101 102 114 110 112 250 251 aa0376 103 111 107 109 108
specifications ac electrical characteristics 2-18 dsp56603/d, preliminary motorola 208 clkout low to rd assertion minimum maximum 0.5 t c + 1.1 0.5 t c + 5.5 9.4 13.8 ns ns 209 clkout low to rd deassertion 0.0 5.5 ns 210 clkout low to wr assertion 3 ws = 1 ? ws 3 ws 3 4 0.5 t c + 6.2 0.5 t c + 6.2 10.1 1.8 10.1 14.5 6.2 14.5 ns 211 clkout low to wr deassertion 0.0 4.9 ns notes: 1. ws is the number of wait states specified in the bcr. 2. the asynchronous delays specified in the expressions are valid for dsp56603-60. 3. if ws>1, wr assertion refers to the next rising edge of clkout. 4. ?xternal bus synchronous timings?should be used only for reference to the clock and not for relative timings. 5. these timings are periodically sampled and are not 100% tested. table 2-12 address trace timings (synchronous and asynchronous) num characteristics expression 60 mhz unit min max 250 address setup time to at assertion 0.5 t c ?4.4 3.9 ? ns 251 at pulse width 0.5 t c ?4.4 3.9 ns 252 clkout low to at assertion 0.75 t c + 5.5 18.0 ns 253 clkout low to at deassertion minimum maximum 0.25 t c + 1.1 0.25 t c + 5.5 5.3 9.7 ns ns note: 1. the address trace (at ) pin is also active on accesses to internal program memory if the address trace enable (ate) bit (bit 15) of the omr is set. in this case, the mcs , rd , and wr signals are deasserted and the data bus is tri-stated while the address bus is driven with the address of the internal access. table 2-11 external bus synchronous timings (sram access) (continued) num characteristics expression 60 mhz unit min max
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-19 ac electrical characteristics host interface timing (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) host port usage considerations careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected. the situation exists in the host port. the considerations for proper operation are discussed below. 1. asynchronous reading of receive byte registers ?hen reading the receive byte registers, rxh or rxl, the host programmer should use figure 2-13 synchronous bus timings sram 1 ws wr rd data out d0?23 clkout data in d0?23 a0?15, mcs at 198 199 252 253 211 210 208 209 206 204 207 203 205 aa0377 202
specifications ac electrical characteristics 2-20 dsp56603/d, preliminary motorola interrupts or poll the rxdf flag, which indicates that data is available. this assures that the data in the receive byte registers will be valid. 2. overwriting transmit byte registers ?he host programmer should not write to the transmit byte registers, txh or txl, unless the txde bit is set indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers can transfer valid data to the hrx register. 3. overwriting the host vector ?he host vector register should be changed only when the host command bit (hc) is clear. this guarantees that the dsp56603 interrupt control logic can receive a stable vector. table 2-13 host interface timing num characteristic symbol expression 60 mhz unit min max 300 access cycle time 4 t c 66.7 ns 301 read data strobe assertion width 5 hack assertion width ? c + 16.5 33.2 ns 302 read data strobe deassertion width 5 hack deassertion width 16.5 ns 303 read data strobe deassertion width between two consecutive ?ast data register?reads, two consecutive cvr reads, two consecutive icr reads, or two consecutive isr reads 3, 5, 8 2.5 t c + 11.0 52.7 ns 304 write data strobe assertion width 6 22.0 ns 305 write data strobe deassertion width 6 2.5 t c + 11.0 52.7 ns 306 has assertion width 16.5 ns 307 has deassertion to data strobe assertion 4 0ns 308 host data input setup time before write data strobe deassertion 6 16.5 ns 309 host data input hold time after write data strobe deassertion 6 5.5 ns 310 read data strobe assertion to output data active from high impedance 5, 10 hack assertion to output data active from high impedance 10 5.0 ns 311 read data strobe assertion to output data valid 5 hack assertion to output data valid 33.0 ns
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-21 312 read data strobe deassertion to output data high impedance 5, 10 hack deassertion to output data high impedance 10 16.5 ns 313 output data hold time after read data strobe deassertion 5 output data hold time after hack deassertion 5.5 ns 314 hcs assertion to read data strobe deassertion t c + 16.5 33.2 ns 315 hcs assertion to write data strobe deassertion 6 16.5 ns 316 hcs assertion to output data valid 27.5 ns 317 hcs hold time after data strobe deassertion 4, 6 0ns 318 address (had0?ad7) setup time before has deassertion (hmux = 1) 7.7 ns 319 address (had0?ad7) hold time after has deassertion (hmux = 1) 5.5 ns 320 ha8?a10 (hmux = 1), ha0?a2 (hmux = 0), hrw setup time before data strobe assertion 4 11.0 ns 321 ha8?a10 (hmux = 1), ha0?a2 (hmux = 0), hrw hold time after data strobe deassertion 4 5.5 ns 322 delay from read data strobe deassertion to host request assertion for ?ast data register? read 5, 7, 8, 9 ? t c + 27.5 60.8 ns 323 delay from write data strobe deassertion to host request assertion for ?ast data register? write 6, 7, 8, 9 1.5 t c + 27.5 52.5 ns 324 delay from data strobe assertion to host request deassertion for ?ast data register?read or write (hrod = 0) 4, 7, 8 27.5 ns 325 delay from data strobe assertion to host request deassertion for ?ast data register?read or write (hrod = 1, open drain host request) 4, 7, 8, 9 300.0 ns table 2-13 host interface timing (continued) num characteristic symbol expression 60 mhz unit min max
specifications ac electrical characteristics 2-22 dsp56603/d, preliminary motorola notes: 1. see host port usage considerations on page 2-19. 2. in the following timing diagrams ( figure 2-14 through figure 2-18 ), the controls pins are drawn as active low. pin polarity is programmable. 3. this timing must be adhered to only if two consecutive reads from one of these registers are executed. 4. the data strobe is hrd or hwr in the dual data strobe mode, hds in the single data strobe mode. 5. the read data strobe is hrd in the dual data strobe mode, hds in the single data strobe mode. 6. the write data strobe is hwr in the dual data strobe mode, hds in the single data strobe mode. 7. the host request is hreq in the single host request mode, hrrq and htrq in the double host request mode. 8. the ?ast data register?is the register at address $7, which is the last location to be read or written in data transfers. 9. in this calculation, the host request signal is pulled up by a 4.7 k w resistor in the open drain mode. 10. these timings are periodically sampled and are not 100% tested. figure 2-14 read timing diagram?on multiplexed bus table 2-13 host interface timing (continued) num characteristic symbol expression 60 mhz unit min max hrd , hds ha0?a2 hcs had0?ad7 hreq 320 314 321 300 301 302 303 316 312 313 311 310 324 325 322 hrrq htrq aa0378 317
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-23 figure 2-15 write timing diagram?on multiplexed bus figure 2-16 host interrupt vector register (ivr) read timing diagram hwd , hds ha0?a2 hcs had0?ad7 hreq 320 315 321 300 304 305 308 309 324 325 323 hrrq htrq aa0379 317 hack had0?ad7 hreq 301 aa0815 313 300 302 312 311 310 303
specifications ac electrical characteristics 2-24 dsp56603/d, preliminary motorola figure 2-17 read timing diagram?ultiplexed bus hrd , hds ha8?a10 hcs had0?ad7 hreq 320 321 300 301 302 303 319 312 313 311 310 324 325 322 hrrq htrq aa0380 306 307 318 data address
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-25 ac electrical characteristics?si0/ssi1 timing (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) figure 2-18 write timing diagram?ultiplexed bus table 2-14 key to table 2-14 ssi timing case meaning t ssicc ssi clock cycle time txc transmit clock (on sck pin) rxc receive clock (on sc0 or sck pin) fst transmit frame sync (on sc2 pin) fsr receive frame sync (sc1 or sc2 pin) i ck internal clock hwd , hds ha8?a10 has had0?ad7 hreq 320 300 304 305 319 309 308 324 325 323 hrrq htrq aa0381 306 307 318 data address
specifications ac electrical characteristics 2-26 dsp56603/d, preliminary motorola x ck external clock i ck a internal clock, asynchronous mode (asynchronous implies that txc and rxc are two different clocks) i ck s internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) bl bit length wl word length wr word length relative table 2-15 ssi timing num characteristics symbol expression 60 mhz case unit min max 430 clock cycle 1 t ssicc 4 t c 3 t c 66.7 50.0 i ck x ck ns ns 431 clock high period for internal clock for external clock 2 t c ?12.2 1.5 t c 21.1 25.0 i ck x ck ns ns 432 clock low period for internal clock for external clock 2 t c ?12.2 1.5 t c 21.1 25.0 i ck x ck ns ns 433 rxc rising edge to fsr out (bl) high 45.1 26.8 x ck i ck a ns ns 434 rxc rising edge to fsr out (bl) low 45.1 26.8 x ck i ck a ns ns 435 rxc rising edge to fsr out (wr) high 3 47.6 29.3 x ck i ck a ns ns 436 rxc rising edge to fsr out (wr) low 3 47.6 29.3 x ck i ck a ns ns 437 rxc rising edge to fsr out (wl) high 45.9 25.6 x ck i ck a ns ns 438 rxc rising edge to fsr out (wl) low 45.1 26.8 x ck i ck a ns ns table 2-14 key to table 2-14 ssi timing (continued) case meaning
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-27 439 data in setup time before rxc (sck in synchronous mode) falling edge 0.0 23.2 x ck i ck ns ns 440 data in hold time after rxc falling edge 6.1 3.6 x ck i ck ns ns 441 fsr input (bl, wr) high before rxc falling edge 3 28.0 1.2 x ck i ck a ns ns 442 fsr input (wl) high before rxc falling edge 28.0 1.2 x ck i ck a ns ns 443 fsr input hold time after rxc falling edge 3.6 0.0 x ck i ck a ns ns 444 flags input setup before rxc falling edge 0.0 23.2 x ck i ck s ns ns 445 flags input hold time after rxc falling edge 7.3 0.0 x ck i ck s ns ns 446 txc rising edge to fst out (bl) high 35.4 18.3 x ck i ck ns ns 447 txc rising edge to fst out (bl) low 37.8 20.7 x ck i ck ns ns 448 txc rising edge to fst out (wr) high 3 37.8 20.7 x ck i ck ns ns 449 txc rising edge to fst out (wr) low 3 40.3 23.2 x ck i ck ns ns 450 txc rising edge to fst out (wl) high 36.6 19.5 x ck i ck ns ns 451 txc rising edge to fst out (wl) low 37.8 20.7 x ck i ck ns ns 452 txc rising edge to data out enable from high impedance 37.8 20.7 x ck i ck ns ns 454 txc rising edge to data out valid 35 + 0.5 t c 52.8 25.6 x ck i ck ns ns 455 txc rising edge to data out high impedance 2 37.8 19.5 x ck i ck ns ns 457 fst input (bl, wr) setup time before txc falling edge 3 2.0 21.0 x ck i ck ns ns table 2-15 ssi timing (continued) num characteristics symbol expression 60 mhz case unit min max
specifications ac electrical characteristics 2-28 dsp56603/d, preliminary motorola 458 fst input (wl) to data out enable from high impedance 2 32.9 x ck i ck ns 460 fst input (wl) setup time before txc falling edge 2.0 21.0 x ck i ck ns ns 461 fst input hold time after txc falling edge 4.0 0.0 x ck i ck ns ns 462 flag output valid after txc rising edge 39.0 22.0 x ck i ck ns ns notes: 1. for internal clock, external clock cycle is defined by i cyc and ssi control register. 2. these timings are periodically sampled and are not 100% tested. 3. the word relative frame sync signal is related to the clock signal as the bit length frame sync signal, but has a period that extends from one serial clock pulse prior to the first bit clock pulse (the same as the bit length frame sync signal) until one serial clock pulse prior to the last bit clock pulse of the first word in the frame. table 2-15 ssi timing (continued) num characteristics symbol expression 60 mhz case unit min max
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-29 figure 2-19 ssi transmitter timing flags out fst (word) in fst (bit) in data out fst (word) out fst (bit) out txc (input/output) first bit last bit note: in the network mode, output flag transitions can occur at the start of each time slot within the frame. in the normal mode, the output flag state is asserted for the entire frame period. 430 431 432 447 450 451 454 452 454 455 461 458 460 461 462 446 457 aa0382
specifications ac electrical characteristics 2-30 dsp56603/d, preliminary motorola figure 2-20 ssi receiver timing flags in fsr (word) in fsr (bit) in data in fsr (word) out fsr (bit) out rxc (input/output) first bit last bit 430 431 432 434 437 438 439 440 443 442 443 442 433 441 aa0383 445
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-31 ac electrical characteristics timer timing (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) table 2-16 timer timing num characteristics symbol expression 60 mhz unit min max 480 tio low ? t c + 2.4 35.7 ns 481 tio high 2 t c + 2.4 35.7 ns 482 timer setup time from tio (input) assertion to clkout rising edge ? c 11.0 16.7 ns 483 synchronous timer delay time from clkout rising edge to the external memory access address out valid, caused by first interrupt instruction execution 10.25 t c + 1.2 172.0 ns 484 clkout rising edge to tio (output) assertion 0.5 t c + 4.3 0.5 t c + 24.2 12.6 32.5 ns 485 clkout rising edge to tio (output) deassertion 0.5 t c + 4.3 0.5 t c + 24.2 12.6 32.5 ns figure 2-21 tio timer event input restrictions tio aa0384 480 481
specifications ac electrical characteristics 2-32 dsp56603/d, preliminary motorola figure 2-22 timer interrupt generation figure 2-23 external pulse generation clkout tio (input) first interrupt instruction execution address 482 483 aa0493 clkout tio (output) 484 485 aa0494
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-33 ac electrical characteristics gpio timing (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) note: gpio timings apply to all gpio signals used on the dedicated gpio pins, hi08 pins, ssi pins, and timer pins. table 2-17 gpio timing num characteristics symbol expression 60 mhz unit min max 490 clkout edge to gpio output valid (gpio out delay time) 37.8 ns 491 clkout edge to gpio output invalid (gpio out hold time) 3.6 ns 492 gpio in valid to clkout edge (gpio in setup time) 14.6 ns 493 clkout edge to gpio input invalid (gpio in hold time) 0.0 ns 494 fetch to clkout edge before gpio change 6.75 t c 112.5 ns figure 2-24 gpio timing valid gpio (input) gpio (output) clkout (output) fetch the instruction move x0,x:(r0); x0 contains the new value of gpio and r0 contains the address of gpio data register a0?15 490 491 492 494 493 aa0384
specifications ac electrical characteristics 2-34 dsp56603/d, preliminary motorola ac electrical characteristics jtag timing (v cc = 3.0 v 0.3 v; t a = ?0? to 85?c, c l = 50 pf + 2 ttl loads) table 2-18 jtag timing num characteristics symbol expression 60 mhz unit min max 500 tck frequency of operation 1/(3 t c ) 0.0 22.0 mhz 501 tck cycle time in crystal mode 45.0 ns 502 tck clock pulse width measured at 1.5 v 20.0 ns 503 tck rise and fall times 0.0 3.0 ns 504 boundary scan input data setup time 5.0 ns 505 boundary scan input data hold time 24.0 ns 506 tck low to output data valid 0.0 40.0 ns 507 tck low to output high impedance 1 0.0 40.0 ns 508 tms, tdi data setup time 5.0 ns 509 tms, tdi data hold time 25.0 ns 510 tck low to tdo data valid 0.0 44.0 ns 511 tck low to tdo high impedance 1 0.0 44.0 ns 512 trst assert time 100.0 ns 513 trst setup time to tck low 40.0 ns 514 de assertion time in order to enter debug mode 1.5 t c + 11.0 36.0 ns 515 response time when dsp56603 is executing nop instructions from internal memory 5.5 t c + 33.0 124.7 ns 516 debug acknowledge assertion time 3 t c + 11.0 61.0 ns note: 1. these timings are periodically sampled and are not 100% tested.
specifications ac electrical characteristics motorola dsp56603/d, preliminary 2-35 figure 2-25 test clock input timing diagram figure 2-26 boundary scan (jtag) timing diagram tck (input) v m v m v ih v il 501 502 502 503 503 aa0496 tck (input) data inputs data outputs data outputs data outputs v ih v il input data valid output data valid output data valid 505 504 506 507 506 aa0497
specifications ac electrical characteristics 2-36 dsp56603/d, preliminary motorola figure 2-27 test access port timing diagram figure 2-28 trst timing diagram figure 2-29 once?ebug request tck (input) tdi (input) tdo (output) tdo (output) tdo (output) v ih v il input data valid output data valid output data valid tms 508 509 510 511 510 aa0498 tck (input) trst (input) 513 512 aa0499 de 516 515 514 aa0500
packaging package and pin-out information this section contains package and pin-out information for the 144-pin thin quad flat pack (tqfp) configuration of the dsp56603. table 3-1 on page 3-4 identifies the dsp56603 pins on the package in numeric order. table 3-2 on page 3-5 identifies the dsp56603 pins by name order. table 3-4 on page 3-11 groups power and ground leads. mechanical drawings of the package are presented in figure 3-3 on page 3-12. complete mechanical information regarding dsp56603 packaging is available by facsimile through motorola's mfax system. call (602) 244-6609 to obtain instructions for using this system. the automated system requests the following information: the receiving fax telephone number including area code or country code the caller? personal identification number (pin) note: for first time callers, the system provides instructions for setting up a pin, which requires entry of a name and telephone number. the type of information requested: instructions for using the system a literature order form specific part technical information or data sheets other information described by the system messages a total of three documents may be ordered per call.
packaging package and pin-out information 3-2 dsp56603/d, preliminary motorola figure 3-1 top view of dsp56603 144-pin plastic thin quad flat package notes: 1. pins marked ?c?are no connection pins that are reserved for possible future enhancements. do not connect these pins to any power, ground, signal traces, or vias. 2. to simplify locating the pins, each fifth pin is shaded in the illustration. orientation mark 109 1 37 73 72 144 36 108 d7 d8 v ccd gnd d d9 d10 d11 d12 d13 d14 v ccd gnd d d15 d16 d17 d18 d19 v ccql gnd q d20 v ccd gnd d d21 d22 d23 modd modc modb moda trst tdo tdi tck tms sc12 sc11 a0 nc mcs nc rd wr gnd c v ccc nc nc nc nc a t clkout gnd c v ccqh v ccql extal gnd q xtal nc nc nc nc gnd p1 gnd p pcap v ccp reset had0 had1 had2 had3 gnd h v cch had4 d6 d5 d4 d3 gnd d v ccd d2 d1 d0 nc nc a15 gnd a v ccqh a14 a13 a12 v ccql gnd q a11 a10 gnd a v cca a9 a8 a7 a6 gnd a v cca a5 a4 a3 a2 gnd a v cca a1 (top view) srd1 std1 sc02 sc01 de pinit/nmi srd0 v ccs gnd s std0 sc10 sc00 gpio0 gpio1 gpio2 sck1 sck0 v ccql gnd q v ccqh hds/hwr hrw/hrd v ccs gnd s tio2 tio1 tio0 ha2/ha9 had7 had6 had5 ha ck/hrrq hreq/htrq hcs/ ha10 ha0/has ha1/ha8
packaging package and pin-out information motorola dsp56603/d, preliminary 3-3 figure 3-2 bottom view of dsp56603 144-pin plastic thin quad flat package notes: 1. pins marked ?c?are no connection pins that are reserved for possible future enhancements. do not connect these pins to any power, ground, signal traces, or vias. 2. to simplify locating the pins, each fifth pin is shaded in the illustration. orientation mark 109 1 37 73 (on top side) (bottom view) a0 nc mcs nc rd wr gnd c v ccc nc nc nc nc a t clkout gnd c v ccqh v ccql extal gnd q xtal nc nc nc nc gnd p1 gnd p pcap v ccp reset had0 had1 had2 had3 gnd h v cch had4 a1 v cca gnd a a2 a3 a4 a5 v cca gnd a a6 a7 a8 a9 v cca gnd a a10 a11 gnd q v ccql a12 a13 a14 v ccqh gnd a a15 nc nc d0 d1 d2 v ccd gnd d d3 d4 d5 d6 had5 had6 had7 tio0 tio1 tio2 gnd s v ccs hds/hwr v ccqh gnd q v cqcl sck0 sck1 gpio2 gpio1 gpio0 sc00 sc10 std0 gnd s v ccs srd0 pinit/nmi de sc01 sc02 std1 srd1 d7 d8 v ccd gnd d d9 d10 d11 d12 d13 d14 v ccd gnd d d15 d16 d17 d18 d19 v ccql gnd q d20 v ccd gnd d d21 d22 d23 modd modc modb moda trst tdo tdi tck tms sc12 sc11 hrw/hrd ha ck/hrrq hreq/htrq hcs/ ha10 ha2/ha9 ha1/ha8 ha0/has
packaging package and pin-out information 3-4 dsp56603/d, preliminary motorola table 3-1 dsp56603 144-pin tqfp pin identification by pin number note: pins marked ?c?in table 3-1 are not connected. up right down left pin # name pin # name pin # name pin # name 144 sc11 108 d6 72 a0 36 had5 143 sc12 107 d5 71 nc 35 had6 142 tms 106 d4 70 mcs 34 had7 141 tck 105 d3 69 nc 33 ha0/has 140 tdi 104 gnd d 68 rd 32 ha1/ha8 139 tdo 103 v ccd 67 wr 31 ha2/ha9 138 trst 102 d2 66 gnd c 30 hcs /ha10 137 moda/irqa 101 d1 65 v ccc 29 tio0 136 modb/irqb 100 d0 64 nc 28 tio1 135 modc/irqc 99 nc 63 nc 27 tio2 134 modd/irqd 98 nc 62 nc 26 gnd s 133 d23 97 a15 61 nc 25 v ccs 132 d22 96 gnd a 60 at 24 hreq /htrq 131 d21 95 v cch 59 clkout 23 hack /hrrq 130 gnd d 94 a14 58 gnd c 22 hrw/hrd 129 v ccd 93 a13 57 v ccqh 21 hds /hwr 128 d20 92 a12 56 v cclq 20 v ccqh 127 gnd q 91 v ccql 55 extal 19 gnd q 126 v ccql 90 gnd q 54 gnd q 18 v ccql 125 d19 89 a11 53 xtal 17 sck0 124 d18 88 a10 52 nc 16 sck1 123 d17 87 gnd a 51 nc 15 gpio2 122 d16 86 v cca 50 nc 14 gpio1 121 d15 85 a9 49 nc 13 gpio0 120 gnd d 84 a8 48 gnd p1 12 sc00 119 v ccd 83 a7 47 gnd p 11 sc10 118 d14 82 a6 46 pcap 10 std0 117 d13 81 gnd a 45 v ccp 9 gnd s 116 d12 80 v cca 44 rese t 8v ccs 115 d11 79 a5 43 had0 7 srd0 114 d10 78 a4 42 had1 6 pinit/nmi 113 d9 77 a3 41 had2 5 de 112 gnd d 76 a2 40 had3 4 sc01 111 v ccd 75 gnd a 39 gnd h 3 sc02 110 d8 74 v cca 38 v cch 2 std1 109 d7 73 a1 37 had4 1 srd1
packaging package and pin-out information motorola dsp56603/d, preliminary 3-5 table 3-2 dsp56603 144-pin tqfp pin identification by pin name name pin # functional group name pin # functional group a0 72 port a address d8 110 port a data a1 73 d9 113 a2 76 d10 114 a3 77 d11 115 a4 78 d12 116 a5 79 d13 117 a6 82 d14 118 a7 83 d15 121 a8 84 d16 122 a9 85 d17 123 a10 88 d18 124 a11 89 d19 125 a12 92 d20 128 a13 93 d21 131 a14 94 d22 132 a15 97 d23 133 at 60 port a control de 5 jtag/once clkout 59 clock/pll extal 55 d0 100 port a data gnd a 75 gnd?ort a address d1 101 gnd a 81 d2 102 gnd a 87 d3 105 gnd a 96 d4 106 gnd c 66 gnd?ort a control d5 107 gnd c 58 d6 108 gnd d 104 gnd?ort a data d7 109 gnd d 112
packaging package and pin-out information 3-6 dsp56603/d, preliminary motorola gnd d 120 gnd?ort a data hcs /ha10 30 peripherals/hi08 gnd d 130 hds /hwr 21 gnd h 39 gnd?i08 data hreq /htrq 24 gnd p 47 gnd?ll hrw/hrd 22 gnd p1 48 mcs 70 port a control gnd q 19 quiet gnd (for both v ccqh and v ccql ) moda/irqa 137 mode/interrupt control gnd q 54 modb/irqb 136 gnd q 90 modc/irqc 135 gnd q 127 modd/irqd 134 gnd s 9 gnd?si, timer, gpio, hi08 control pcap 46 clock/pll gnd s 26 pinit/nmi 6 gpio0 13 peripherals/gpio rd 68 port a control gpio1 14 reset 44 gpio2 15 sc00 12 peripherals/ssi0 ha0/has 33 peripherals/hi08 sc01 4 ha1/ha8 32 sc02 3 ha2/ha9 31 sc10 11 peripherals/ssi1 hack /hrrq 23 sc11 144 had0 43 sc12 143 had1 42 sck0 17 peripherals/ssi0 had2 41 sck1 16 peripherals/ssi1 had3 40 srd0 7 peripherals/ssi0 had4 37 srd1 1 peripherals/ssi1 had5 36 std0 10 peripherals/ssi0 had6 35 std1 2 peripherals/ssi1 had7 34 tck 141 jtag/once table 3-2 dsp56603 144-pin tqfp pin identification by pin name (continued) name pin # functional group name pin # functional group
packaging package and pin-out information motorola dsp56603/d, preliminary 3-7 note: the 12 pins marked as ?c?are reserved for possible future enhancements. do not connect these pins to any power, signal, or ground traces or vias. tdi 140 jtag/once v cch 38 v cc ?i08 data tdo 139 v ccp 45 v cc ?ll tio0 29 peripherals/timer v ccqh 20 quiet v cc high tio1 28 v ccqh 57 tio2 27 v ccqh 95 tms 142 jtag/once v ccql 18 quiet v cc low trst 138 v ccql 56 v cca 74 v cc ?ort a address v ccql 91 v cca 80 v ccql 126 v cca 86 v ccs 8v cc ?si, timer, gpio, hi08 control v ccc 65 v cc ?ort a control v ccs 25 v ccd 103 v cc ?ort a data wr 67 port a control v ccd 111 xtal 53 clock/pll v ccd 119 nc 49,50,51,52,61, 62, 63, 64, 69, 71, 98, 99 v ccd 129 table 3-2 dsp56603 144-pin tqfp pin identification by pin name (continued) name pin # functional group name pin # functional group
packaging package and pin-out information 3-8 dsp56603/d, preliminary motorola table 3-3 dsp56603 functional signal groups (144 tqfp) name pin # functional group name pin # functional group a0 72 core/port a address d10 114 core/port a data a1 73 d11 115 a2 76 d12 116 a3 77 d13 117 a4 78 d14 118 a5 79 d15 121 a6 82 d16 122 a7 83 d17 123 a8 84 d18 124 a9 85 d19 125 a10 88 d20 128 a11 89 d21 131 a12 92 d22 132 a13 93 d23 133 a14 94 at 60 core/port a ctrl a15 97 mcs 70 d0 100 core/port a data moda/irqa 137 d1 101 modb/irqb 136 d2 102 modc/irqc 135 d3 105 modd/irqd 134 d4 106 rd 68 d5 107 wr 67 d6 108 v cca 74 core/v cc port a address d7 109 v cca 80 d8 110 v cca 86 d9 113 v ccc 65 core/v cc port a ctrl
packaging package and pin-out information motorola dsp56603/d, preliminary 3-9 v ccd 103 core/v cc for port a data tms 142 core/jtag v ccd 111 trst 138 v ccd 119 had0 43 peripherals/hi08 v ccd 129 had1 42 gnd a 75 core/gnd for port a address had2 41 gnd a 81 had3 40 gnd a 87 had4 37 gnd a 96 had5 36 gnd c 58 core/gnd port a control had6 35 gnd c 66 had7 34 gnd d 104 core/gnd for port a data ha0/has 33 gnd d 112 ha1/ha8 32 gnd d 120 ha2/ha9 31 gnd d 130 hcs /ha10 30 clkout 59 core/pll hack /hrrq 23 extal 55 hds /hwr 21 pcap 46 hreq /htrq 24 pinit/nmi 6 hrw/hrd 22 xtal 53 v cch 38 peripherals/v cc hi08 v ccp 45 core/v cc for pll gnd h 39 peripherals/gnd hi08 gnd p 47 core/gnd for pll sc00 12 peripherals/ssi0 gnd p1 48 sc01 4 de 5 core/jtag sc02 3 tck 141 sck0 17 tdi 140 srd0 7 tdo 139 std0 10 table 3-3 dsp56603 functional signal groups (144 tqfp) (continued) name pin # functional group name pin # functional group
packaging package and pin-out information 3-10 dsp56603/d, preliminary motorola note: the 12 pins marked as ?c?are reserved for possible future enhancements. do not connect these pins to any power, signal, or ground traces or vias. power and ground pins have special considerations for noise immunity. see electrical design considerations , on page 4-3, for more information. sc10 11 peripherals/ssi1 gnd s 9 peripherals/gnd for ssi0, ssi1, timer, gpio sc11 144 gnd s 26 sc12 143 v ccqh 20 quiet v cc high sck1 16 v ccqh 57 srd1 1 v ccqh 95 std1 2 v ccql 18 quiet v cc low tio0 29 peripherals/timer v ccql 56 tio1 28 v ccql 91 tio2 27 v ccql 126 gpio0 13 peripherals/gpio gnd q 19 quiet ground (for both v ccqh and v ccql ) gpio1 14 gnd q 54 gpio2 15 gnd q 90 v ccs 8 peripherals/v cc for ssi0, ssi1, timer, gpio gnd q 127 v ccs 25 nc 49, 50, 51, 52, 61, 62, 63, 64, 69, 71, 98, 99 table 3-3 dsp56603 functional signal groups (144 tqfp) (continued) name pin # functional group name pin # functional group
packaging package and pin-out information motorola dsp56603/d, preliminary 3-11 table 3-4 dsp56603 144-pin tqfp power supply pins name pin # functional group name pin # functional group v cca 74 core/port a address v ccd 103 core/port a data v cca 80 v ccd 111 v cca 86 v ccd 119 gnd a 75 v ccd 129 gnd a 81 gnd d 104 gnd a 87 gnd d 112 gnd a 96 gnd d 120 v ccc 65 core/port a control gnd d 130 gnd c 66 v ccp 45 core/pll gnd c 58 gnd p 47 v ccqh 20 quiet v cc high gnd p1 48 v ccqh 57 gnd q 19 quiet gnd (for both v ccqh and v ccql ) v ccqh 95 gnd q 54 v cclq 18 quiet v cc low gnd q 90 v ccql 56 gnd q 127 v ccql 91 v cch 38 peripherals/hi08 data v ccql 126 gnd h 39 gnd s 9 peripherals/ssi0, ssi1, timer, gpio, hi08 control v ccs 8 peripherals/ssi0, ssi1, timer, gpio, hi08 control gnd s 26 v ccs 25
packaging package and pin-out information 3-12 dsp56603/d, preliminary motorola figure 3-3 144-pin thin quad flat pack (tqfp) mechanical information seating plane 0.1 t 144x c 2 q view ab 2 q t plating f aa j d base metal section j1-j1 (rotated 90) 144 pl m 0.08 n t l? n 0.20 t l? 144 73 109 37 108 1 36 72 4x 4x 36 tips pin 1 ident view y b b1 v1 a1 s1 v a s n 0.20 t l? m l n p 4x g 140x j1 j1 view y c l x x=l, m or n gage plane q 0.05 (z) r2 e c2 (y) r1 (k) c1 1 q 0.25 view ab dim min max millimeters a 20.00 bsc a1 10.00 bsc b 20.00 bsc b1 10.00 bsc c 1.40 1.60 c1 0.05 0.15 c2 1.35 1.45 d 0.17 0.27 e 0.45 0.75 f 0.17 0.23 g 0.50 bsc j 0.09 0.20 k 0.50 ref p 0.25 bsc r1 0.13 0.20 r2 0.13 0.20 s 22.00 bsc s1 11.00 bsc v 22.00 bsc v1 11.00 bsc y 0.25 ref z 1.00 ref aa 0.09 0.16 q 0 q 0 7 q 11 13 1 2 notes: 1. dimensions and tolerancing per asme y14.5-1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not inculde mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 6. dimension d does not include dambar protrusion. allowabled dambar protrusion shall not cause the d dimension to exceed 0.35. case 918-03
motorola dsp56603/d, preliminary 4-1 section 4 design considerations thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature ?c r q ja = package junction-to-ambient thermal resistance ?c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to- case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance ?c/w r q jc = package junction-to-case thermal resistance ?c/w r q ca = package case-to-ambient thermal resistance ?c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. again, t j t a p d r q ja () + = r q ja r q jc r q ca + =
design considerations thermal design considerations 4-2 dsp56603/d, preliminary motorola if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. this is done to minimize temperature variation across the surface. measure the thermal resistance from the junction to where the leads are attached to the case. this definition is approximately equal to a junction to board thermal resistance. use the value obtained by the equation (t j ?t t )/p d where t t is the temperature of the package case determined by a thermocouple. as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual. hence, the new thermal metric, thermal characterization parameter, or y jt , has been defined to be (t j ? t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. note: table 2-3 package thermal characteristics on page 2-2 contains the package thermal values for this chip.
design considerations electrical design considerations motorola dsp56603/d, preliminary 4-3 electrical design considerations each v cc pin on the dsp56603 should be provided with a low-impedance path to the board? supply. each gnd pin should likewise be provided with a low- impedance path to ground. the power supply pins drive distinct groups of logic on-chip as shown in table 1-2 power inputs on page 1-3 and table 1-3 grounds on page 1-4. for best results, separate v cc and gnd for each supply is recommended; each with a capacitor to bypass v cc to gnd as close as possible to the package. otherwise, a multi-layer board is recommended, employing two inner layers as v cc and gnd planes. two 0.1 m f ceramic capacitors as close as possible to each side of the package (eight capacitors altogether) should be used to bypass the v cc power supply layer to the ground layer. in such cases, there is no separation between the various power and ground supplies, since each one is directly tied to the appropriate plane. therefore, the capacitors are common to all the v cc /gnd pairs. the v cc /gnd supplies of the pll should be well-regulated (non-switching regulators), and the pins should be provided with an extremely low impedance path to v cc /gnd. it is recommended that v ccp should be connected to the main power supply with a special power branch. if required, filtering circuitry should be provided. if v ccp and gnd p are kept separate from the other supplies, an additional larger capacitor (e.g., 47 m f) should be used between these pins. an additional large capacitor should be placed next to the power supply itself. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ).
design considerations electrical design considerations 4-4 dsp56603/d, preliminary motorola all output pins on the dsp56603 have fast rise and fall times. printed circuit board (pcb) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses, as well as to the port a control signals and port b pins. maximum pcb trace lengths on the order of 6 inches (15.24 cm) are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pcb traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. drive to a valid value (e.g., connect to pull-up or pull-down resistors) all unused inputs or signals that will be inputs during reset (reset asserted). every input pin should be driven to a valid value after the reset deassertion by connecting it to a pull-up or pull-down resistor if not used. exceptions to this are the trst , de , and tms pins, which have internal pull-up resistors. the reset and trst pins must be asserted low after power-up. all this data relates to a single dsp56603. if multiple dsp56603 devices are on the same board, check for cross-talk or excessive spikes on the supplies caused by synchronous operation of the devices.
design considerations power consumption considerations motorola dsp56603/d, preliminary 4-5 power consumption considerations power dissipation is a key issue in portable dsp applications. this section describes some of the factors that affect current consumption. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. therefore, the total current consumption is the sum of these internal and external currents. this current consumption is described by the formula: equation 3: i = c v ? f where: c = node/pin capacitance (in farads) v = voltage swing (in volts) f = frequency of node/pin toggle (in hz) the typical internal current value (i cci ) reflects the typical switching of the internal buses in a typical dsp-intensive application. for applications requiring very low current consumption, it is recommended to: set the pcd bit (in the omr) and do not use the pc-relative instructions. set the ebd bit (in the omr) when not accessing external memory minimize external memory accesses and use internal memory accesses instead minimize the number of pins that are switching minimize the capacitive load on the pins connect the unused inputs to pull-up or pull-down resistors. disable unused peripherals disable unused pin activity (e.g., clkout, xtal) a common way to evaluate power consumption is to use a current per mips measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the dsp). a benchmark power consumption test algorithm is listed in appendix a . use the test algorithm and example 4-1 current consumption for a port a address pin loaded with 50 pf capacitance, operating at 2.7 v, and with a 60 mhz clock, toggling at its maximum possible rate of 15 mhz, the current consumption is (for this pin only): equation 4: i = 50 10 - 12 ? 2.7 15 ? 10 6 = 2.025 ma
design considerations pll performance issues 4-6 dsp56603/d, preliminary motorola measure the current consumption at two different frequencies, f1 and f2. then use the following equation to derive the current per mips value: equation 5: where: i typf2 = current at f2 i typf1 = current at f1 f2 = high frequency (any specified operating frequency) f1 = low frequency (any specified operating frequency lower than f2) note: f1 should be significantly less than f2. for example, f2 could be 60 mhz and f1 could be 30 mhz. the degree of difference between f1 and f2 determines the amount of precision with which the current rating can be determined for an application. pll performance issues the following explanations are provided as general observations on expected pll behavior. measurements are preliminary and are subject to change. phase skew performance the phase skew of the pll is defined as the time difference between the falling edges of extal and clkout for a given capacitive load on clkout, over the entire process, temperature and voltage ranges. for input frequencies greater than 15 mhz and mf ? 4, this skew is greater than or equal to 0.0 ns and less than 1.8 ns; otherwise, this skew is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this skew is between ?.4 ns and +3.2 ns. phase jitter performance the phase jitter of the pll is defined as the variations in the skew between the falling edges of extal and clkout for a given device in specific temperature, voltage, input frequency, mf, and capacitive load on clkout. these variations are a result of the pll locking mechanism. for input frequencies greater than 15 mhz and mf ? 4, this jitter is less than 0.6 ns; otherwise, this jitter is not guaranteed. however, for mf < 10 and input frequencies greater than 10 mhz, this jitter is less than 2 ns. i mips i mhz i typf2 i typf1 () f2 f1 () ==
design considerations pll performance issues motorola dsp56603/d, preliminary 4-7 frequency jitter performance the frequency jitter of the pll is defined as the variation of the frequency of clkout. for small mf (mf < 10) this jitter is smaller than 0.5%. for mid-range mf (10 < mf < 500) this jitter is between 0.5% and approximately 2%. for large mf (mf > 500), the frequency jitter is 2 - 3%. input (extal) jitter requirements the allowed jitter on the frequency of extal is 0.5%. if the rate of change of the frequency of extal is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time) then the allowed jitter can be 2%. the phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values.
design considerations pll performance issues 4-8 dsp56603/d, preliminary motorola
motorola dsp56603/d, preliminary 5-1 section 5 ordering information table 5-1 lists the pertinent information needed to place an order. consult a motorola semiconductor sales office or authorized distributor to determine availability and to order parts. table 5-1 dsp56603 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56603 3.0 v plastic thin quad flat pack (tqfp) 144 60 dsp56603pv60
ordering information 5-2 dsp56603/d, preliminary motorola
motorola dsp56603/d, preliminary a-1 appendix a power consumption benchmark the following benchmark program permits evaluation of dsp power usage in a test situation. it enables the pll. then it disables the xtal generation, external clkout generation, external port, and pc-relative instructions. finally it uses repeated multiply-accumulate (mac) instructions with a set of synthetic dsp application data to emulate intensive sustained dsp operation. this synthetic benchmark provides a structure and performance that is similar to a typical dsp-intensive algorithm, as used in the target cellular subscriber market. a typical target application consumes approximately 90% of the current used by this benchmark program. the two listed equate files, ioequ.asm and intequ.asm, are available in print format in appendix b of the dsp56603 user? manual, dsp56603um/ad , as well as electronically via the internet on the motorola dsp home page. the web page address is provided on the back page of this document. int_prog equ $0 ; internal program memory ; starting address int_xdat equ $0 ; internal x-data memory ; starting address int_ydat equ $0 ; internal y-data memory include "ioequ.asm" include "intequ.asm" list org p:int_prog movep #$d0,x:m_pctl1 ; xtal disable ; pll enable ; clkout disable ori #$10,omr ; set ebd ori #$20,omr ; set pcd prog_start move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 clr a clr b
power consumption benchmark a-2 dsp56603/d, preliminary motorola move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 do forever, _end ; main loop mac x0,y0,a x:(r0)+,x1 y:(r4)+,y1 mac x1,y1,a x:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,a x:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end nop nop org x:xdat_start dc $2eb9 dc $f2fe dc $6a5f dc $6cac dc $fd75 dc $10a dc $6d7b dc $a798 dc $fbf1 dc $63d6 dc $6657 dc $a544 dc $662d dc $e762 dc $f0f3 dc $f1b0 dc $829 dc $f7ae dc $a94f dc $78dc dc $2de5 dc $e0ba dc $ab6b dc $26c8 dc $361 dc $6e86 dc $7347 dc $e774 dc $349d dc $ed12 dc $fce3 dc $26e0 dc $7d99 dc $a85e dc $a43f
power consumption benchmark motorola dsp56603/d, preliminary a-3 dc $b10c dc $a55 dc $ec6a dc $255b dc $f1f8 dc $26d1 dc $6536 dc $bc37 dc $35a4 dc $f0d dc $bec2 dc $e4d3 dc $e810 dc $f09 dc $e50e dc $fb2f dc $753c dc $62c5 dc $641a dc $3b4b dc $a928 dc $6641 dc $a7e6 dc $2127 dc $2fd4 dc $57d dc $3c72 dc $8c3 dc $7540 org y:ydat_start dc $6da dc $f70b dc $39e8 dc $e801 dc $66a6 dc $f8e7 dc $ec94 dc $233d dc $2732 dc $3c83 dc $3e00 dc $b639 dc $a47e dc $fddf dc $a2c dc $7cf5 dc $6a8a dc $b8fb dc $ed18 dc $f371 dc $a556 dc $e9d7
power consumption benchmark a-4 dsp56603/d, preliminary motorola dc $a2c4 dc $35ad dc $e0e2 dc $2c73 dc $2730 dc $7fa9 dc $292e dc $3ccf dc $a65c dc $6d65 dc $a3a dc $b6eb dc $ac48 dc $7ae1 dc $3006 dc $f6c7 dc $64f4 dc $e41d dc $2692 dc $3863 dc $bc60 dc $a519 dc $39de dc $f7bf dc $3e8c dc $79d5 dc $f5ea dc $30db dc $b778 dc $fe51 dc $a6b6 dc $ffb7 dc $f324 dc $2e8d dc $7842 dc $e053 dc $fd90 dc $2689 dc $b68e dc $2eaf dc $62bc dc $a245 ; end of program
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